A continuing objective of integrated circuit designs in closer spacing (higher integration density) of the respective components of which a circuit configuration is made, in order to increase signal processing speed and occupation area per wafer (more circuits per chip). To meet this objective, semiconductor processing engineers have continued to refine wafer processing methodologies, particularly the patterning techniques through which individual regions of the semiconductor structure are defined. In order to pack a larger number of components in the semiconductor structure, integrated circuit configurations have evolved into complex three dimensional topographies comprised of the wafer material itself (e.g. silicon, gallium arsenide) and a multilevel dielectric (e.g. silicon dioxide, phosphosilicate glass)/interconnect (e.g. aluminum, gold doped polysilicon) overlay.
For realizing an intended structural configuration, the respective layers of which the integrated circuit is made are selectively patterned, typically employing a series of mask and etch steps. In accordance with such processing, one or more layers of material to be patterned (selectively removed) is covered with a relatively thin layer (on the order of 15,000 .ANG.) of photoresist. Selected areas of the photoresist layer that are to serve as apertures for etching the underlying structure are exposed to light through a photoresist mask. The photoresist is developed and washed to remove those portions of the photoresist layer that had not been masked. It is through these apertures in the photoresist layer that the underlying semiconductor structure is removed (etched). While this process has been generally adequate for relatively simple integrated circuit topographies, it has been found to entail a number of shortcomings when applied to very narrow line width (on the order of two micron or less), undulating multilevel semiconductor structures (e.g. high complexity very high speed integrated circuit topographies).
More particularly, where the material underlying the photoresist is highly reflective (e.g. a metallic interconnect layer of gold or aluminum) the light which passes into an intended region of the photoresist through the mask may reflect off the underlying reflective interface and travel through portions of the photoresist layer not intended to be activated by the light. This is particularly true where the reflective interface is not normal to the direction of incidence of the light beam. For a relatively thin layer of photoresist the reflected light may contain sufficient energy to effectively enlarge the size of the intended aperture, creating what is termed "reflective notching" of the photoresist layer.
Another problem in using a thin layer of photoresist is its inability to provide adequate step coverage. Namely, at sharply sloped portions of the underlying semiconductor structure the thickness of the photoresist may be significantly decreased or tapered relative to other portions. As a result, during its subsequent use as an etchant mask for removing underlying material exposed by the apertures in the photoresist mask, (during which time the photoresist is also attacked by the etchant) these relatively thin portions may be completely removed, thereby exposing previously masked surface areas of the underlying structure to the etchant.
A further disadvantage of the poor step coverage provided by a thin photoresist layer is the substantial height differential of respective areas of the three dimensional surface of the resulting topography. This height differential (which may be on the order of two to four microns) is often larger than the depth of focus of the imaging optics of the photolithographic equipment employed to selectively expose the photoresist layer. As a result, an imprecise image is created on the photoresist layer.
In an attempt to obviate the above-described problems of conventional single layer photoresist processing, a number of multi-layer masking techniques have been proposed. These include incorporating multiple layers of different compositions (e.g. photoresist-glass-polymer, metallic inner layers, as described for example in Fraser et al U.S. Pat. No. 4,244,799 and Griffing U.S. Pat. No. 4,362,598) or thickening the layer of photoresist in an attempt to planarize its top surface (as described for example in Horst et al U.S. Pat. No. 3,873,313, White et al U.S. Pat. No. 4,427,713 and Reichmanis et al U.S. Pat. No. 4,481,049). Unfortunately these proposals are either complicated from a standpoint of the use of diverse materials or they constitute only a partial solution to the problem. For example, thickening the photoresist layer, per se, as proposed by the White et al U.S. Pat. No. 4,427,713, while improving step coverage, does not eliminate the notching problem; the thicker photoresist layer is still effectively patterned using a conventional exposure and etch process for etching a top resist mask, creating the problem of undercutting and enlarging the apertured portion of the thick photoresist layer.